AI is driving simultaneous increases in data movement and electricity demand, making optical connectivity a strategic efficiency layer.
The Global Silicon Photonics Market is estimated at USD 2.15 billion in 2024, reaching USD 2.75 billion in 2025 and USD 3.35 billion in 2026.
The market is projected to reach USD 14.19 billion by 2033, reflecting a 22.9% CAGR during 2026–2033.
Market expansion is being driven primarily by the increasing optical bandwidth requirements of AI infrastructure, hyperscale data centers, and high-performance computing. Optical links provide higher bandwidth and longer reach than electrical interconnects, and industry development is increasingly moving optical connectivity from conventional pluggable modules toward board-level and package-level architectures. Imec identifies data movement between processing units as a critical bottleneck for AI workloads. At the same time, Intel's commercial deployment history demonstrates that silicon photonics has already progressed beyond the experimental stage into high-volume data-center networking.
AI Infrastructure Is Increasing Demand for Optical Interconnects
The expansion of AI computing is changing the economics of data-center connectivity. As AI clusters incorporate more accelerators, the amount of data exchanged among processors, switches, and memory increases rapidly. The International Energy Agency projects global data-center electricity consumption to reach approximately 945 TWh by 2030, compared with roughly 415 TWh in 2024, while electricity consumption from accelerated servers is projected to grow at around 30% annually in its base case.
This creates a dual requirement: greater bandwidth and lower energy consumption per transmitted bit. Electrical connections remain highly effective at short distances, but their power and signal-integrity limitations become increasingly important as bandwidth and reach increase. Imec notes that optical links already provide increased bandwidth, longer reach and lower latency and identifies data movement between processing units as a critical bottleneck for AI workloads.
The resulting opportunity extends beyond conventional data-center networking. Optical connectivity is increasingly being considered for scale-up networks connecting accelerators, scale-out networks connecting racks, and eventually optical links within advanced packages. Silicon photonics therefore benefits from the structural growth of AI infrastructure rather than from a single generation of optical transceivers.
Rising Data Rates Are Moving Silicon Photonics Toward 1.6T and Beyond
Data-rate increases are becoming a central driver of technology. Intel's commercial silicon-photonics portfolio includes 400 Gbps, 800 Gbps, and 1.6 Tbps solutions. At the same time, its Optical Compute Interconnect roadmap begins at 4 Tbps of bidirectional bandwidth per chiplet and extends toward tens of terabits per second per device.
TSMC reports that its 65nm silicon-photonics technology is already in volume production and that it is developing 3D-stacking technology to integrate silicon photonics with high-performance computing for CPO applications. TSMC has also demonstrated 200Gbps optical signal modulation and greater than 99% 3D-stacking yield on engineering samples.
The commercial implication is significant. As data rates increase, optical connectivity cannot simply scale by increasing the number of conventional electrical interfaces. Higher-speed architectures increasingly require greater optical bandwidth density, improved signal integrity, and shorter electrical paths. This favors silicon-photonics platforms capable of integrating photonic and electronic functions at wafer and package level.
Power per Bit Is Becoming a Core Technology Selection Criterion
The value proposition of silicon photonics is shifting from speed alone toward performance per watt. The increasing electricity requirements of AI infrastructure make the power consumed by networking and data movement a material operating consideration.
NVIDIA's silicon-photonics CPO platforms illustrate this transition. The company reports that its CPO-based networking architecture delivers approximately 5x higher network power efficiency than traditional pluggable-transceiver approaches. NVIDIA's Spectrum-X Photonics architecture provides up to 409.6 Tbps of total bandwidth and integrates optical engines directly with the switching ASIC.
The opportunity is therefore not simply to transmit more data. It is to transmit more data while limiting the incremental energy required for each additional unit of bandwidth. This creates a growing advantage for architectures that shorten electrical paths, reduce conversion losses, and integrate optics closer to the compute or switching silicon.
Co-Packaged Optics Is Expanding the Addressable Silicon Photonics Opportunity
The silicon-photonics market is transitioning from pluggable optics tonear-packaged and co-packaged optics. In conventional pluggable architectures, electrical signals travel between the switch ASIC and optical module before being converted into optical signals. CPO moves the optical engine closer to the switch ASIC, reducing the length of high-speed electrical paths.
Broadcom's third-generation CPO platform, announced in 2025, supports 200G per optical lane and incorporates improvements in OSAT processes, thermal design, fiber routing, and manufacturing yield.
NVIDIA has similarly moved silicon photonics into commercial networking architectures, announcing the Spectrum-X Photonics and Quantum-X Photonics platforms, both designed around CPO. Its Spectrum-X Photonics architecture uses 1.6 Tbps-per-port connectivity and is designed to scale AI infrastructure toward million-GPU systems.
CPO therefore represents a structural opportunity for silicon photonics because it increases the amount of optical functionality per high-performance switch rather than simply increasing the number of conventional optical modules.
Advanced Packaging Is Emerging as a Market Bottleneck
The limiting factor for silicon photonics is increasingly moving beyond the photonic circuit itself. Advanced packaging must simultaneously address optical coupling, thermal management, fiber routing, electrical signal integrity, manufacturing yield, and serviceability.
Broadcom's CPO development highlights the importance of OSAT processes, thermal design, handling and yield in moving CPO toward commercial deployment. GlobalFoundries similarly identifies 2.5D/3D integration, wafer-level testing and advanced packaging as core elements of its silicon-photonics platform. Its technology supports 200G/λ, with a path toward 400G/λ, alongside CPO and NPO architectures.
This creates an important competitive shift. Silicon-photonics companies increasingly require access to semiconductor foundries, advanced packaging capacity, and qualified manufacturing ecosystems. As a result, the market is likely to favor companies capable of controlling or coordinating multiple stages of the photonic value chain.
The economics of silicon photonics increasingly depend on the amount of bandwidth delivered per unit of power, package area, and manufacturing cost. In modern hyperscale data centers, optical interconnects already account for a meaningful share of system power consumption, with high-speed optical transceivers typically consuming 3–15 watts per 400G–800G module, depending on reach and DSP architecture. Industry analyses from hyperscalers and component vendors indicate that as AI clusters scale beyond tens of thousands of accelerators, interconnect power can account for 10–20% of total data-center power draw, making bit-level efficiency improvements increasingly critical. Imec has identified future optical interconnect requirements including multi-Tbps/mm bandwidth density, power consumption below 5 pJ/bit, link latency below 100 ns, and cost targets of 10 cents/Gbps or less for emerging AI-oriented optical interconnects.
These requirements indicate why the market is progressing toward integration. For example, current 800G pluggable optical modules occupy a full front-panel slot and require separate DSP, laser, and driver components. In contrast, emerging co-packaged optics (CPO) architectures integrate optical engines directly alongside switch ASICs, reducing electrical trace lengths that can exceed 10–20 cm in pluggable designs to just a few millimeters in CPO implementations. This reduction in electrical distance directly lowers signal loss and can reduce interconnect power consumption by 30–50% in early CPO deployments, according to vendor roadmaps from Broadcom and NVIDIA.
At the system level, hyperscale operators such as Meta, Google and Microsoft are already deploying 400G and 800G optical links at rack scale, with early trials of 1.6T-class interconnects underway for AI training clusters. In these environments, even a 1 pJ/bit improvement translates into megawatt-scale savings when scaled across millions of active optical lanes. As a result, simply increasing the number of discrete optical modules increases not only power and space requirements but also cooling and service complexity at the rack and row level.
By moving photonic engines closer to switching and computing silicon, manufacturers can reduce electrical-path losses, improve signal integrity at higher data rates (800G–1.6T and beyond), and increase bandwidth density per square millimeter of package area. This architectural shift is also enabling new system designs such as scale-up AI fabrics with sub-microsecond latency targets, which are becoming essential for distributed GPU training workloads where synchronization overhead directly impacts model training efficiency.
The economic advantage therefore becomes more pronounced as bandwidth requirements rise. At 400G, conventional pluggable architectures remain commercially attractive because of their maturity and serviceability. At 800G and 1.6T, however, power and density become more significant constraints, strengthening the case for LPO, NPO and CPO architectures.
Regional attractiveness is increasingly determined by the combination of AI infrastructure investment, semiconductor manufacturing capabilities, photonics R&D, advanced packaging and hyperscaler presence rather than by telecommunications infrastructure alone.
North America has the strongest combination of hyperscaler demand, AI infrastructure investment, semiconductor investment and silicon-photonics commercialization. Intel, NVIDIA, Broadcom and
GlobalFoundries are developing technologies spanning silicon photonics, optical I/O and CPO. GlobalFoundries announced a proposed USD 300 million U.S. CHIPS R&D award in 2026 to advance silicon-photonics wafer technologies, optical materials and advanced packaging.
Asia-Pacific combines major semiconductor manufacturing capacity with advanced packaging and optical-component ecosystems. TSMC's volume production of silicon photonics and development of 3D-stacked CPO illustrate the region's strategic importance.
Europe has strong photonics research and semiconductor development capabilities, with organizations such as imec contributing to 300mm silicon-photonics platforms and next-generation optical interconnect research.
The resulting framework places North America and Asia-Pacific as the strongest near-term commercial regions, while Europe remains strategically important for photonics research, advanced manufacturing and technology development.
The silicon-photonics supply chain spans silicon wafers and CMOS foundries, photonic integrated circuits (PICs), III–V laser sources (typically InP-based), silicon modulators, electronic drivers and TIAs, advanced optical packaging, fiber-array coupling, optical engines, and full transceiver or co-packaged switching systems. According to Yole Group, optical transceiver revenue exceeded USD 12 billion in 2023, with silicon photonics accounting for a rapidly growing share driven by 400G and 800G deployments in hyperscale data centers.
The value chain is becoming increasingly vertically integrated. Intel has shipped over 8 million silicon photonic PICs and 32 million integrated lasers for data-center optics, while Broadcom and NVIDIA are actively integrating silicon photonics into co-packaged optics (CPO) switch platforms targeting 200G per lane and 51.2 Tbps–102.4 Tbps switch systems. TSMC’s silicon photonics platform is already in volume production on 65nm processes, with demonstrated 200 Gbps optical modulation and active development of 3D-integrated CPO packaging. GlobalFoundries is scaling its 300mm silicon photonics platform to support 200G/λ, witha roadmap toward 400G/λ.
The key constraint is shifting from wafer fabrication to system integration. Industry data from LightCounting indicates that optical module demand is growing at ~20–25% CAGR, but advanced packaging capacity (OSATs), laser supply (InP epitaxy), and high-yield fiber coupling remain critical bottlenecks. As a result, firms with control over packaging ecosystems, laser integration, and hyperscale qualification cycles are increasingly capturing disproportionate value versus pure-play photonic component suppliers.
The most material risks stem from the speed at which new optical architectures move from demonstration to volume production. CPO offers significant theoretical and demonstrated advantages in power and bandwidth, but its commercial adoption depends on packaging yield, thermal management, manufacturing reliability, and system-level serviceability.
Key companies participating across the global silicon-photonics and optical-interconnect ecosystem include Intel, NVIDIA, Broadcom, TSMC, GlobalFoundries, Coherent, Lumentum, Marvell, Cisco, Fabrinet, Ayar Labs and other specialized photonics and optical-component companies.
Competition is increasingly extending beyond photonic-device performance to encompass the ability to integrate silicon-photonics process technology, optical engines, electrical ICs, advanced packaging, and system-level networking.
NVIDIA's development of Spectrum-X and Quantum-X Photonics demonstrates the movement of silicon photonics into the networking-system layer, while Broadcom is advancing CPO at the switch-ASIC level. Intel is extending its silicon-photonics platform into optical compute interconnect, and TSMC and GlobalFoundries are strengthening the manufacturing and packaging infrastructure required to commercialize these architectures.